This invention generally relates to integrating analog signals, and more particularly to a circuit for regulating the output of an electronic integrator. The invention also relates to an analog-to-digital converter having an overflow compensation circuit which regulates the output of an electronic integrator connected to the analog-to-digital converter.
Integrators have proven useful in many applications which require the generation or processing of analog signals. These applications include computed-tomography (CT) machines, nuclear systems, analog-to-digital converters, and various types of sensors. An integrator is conventionally formed from a capacitor connected between the inverting terminal and the output terminal of an operational amplifier. In operation, a current/voltage signal is input into the inverting terminal and the operational amplifier outputs a signal which corresponds to the integral of the input.
In circuits of this type, a linear relationship exists between the input charge and the output voltage as long as the operational amplifier is in its active region. This relationship may be represented by the equation Qin=CintVout, where Qin is the input charge, Cint is the integrating capacitor, and Vout is the output voltage. From this equation, it is clear that the integrating capacitor can store only a finite amount of charge before the operational amplifier becomes saturated. For maximum gain, Cint is designed to be as small as possible. Therefore, in order to accommodate a large dynamic range of input charge, conventional integrators typically use banks of integrating capacitors, which may either be pre selected or dynamically selected to preserve the linear relationship between the input charge and the output voltage.
Medical systems and other applications integrate data signals over certain periods of time. It has been determined that interruptions during these periods, even minor ones, degrade the accuracy of the integrator output, and this, in turn, translates into inaccuracies in the overall system.
One interruption that routinely occurs derives from the use of conventional integrators. In these integrators, the expected value of the integrated signal is intended to average zero. Certain circumstances, however, inevitably arise which cause the integrator to output signals which reach unacceptable positive or negative levels. In order to correct this problem, conventional integrators must be periodically reset to zero or some other reference value.
In view of the foregoing considerations, it would be highly desirable to provide an integrator which does not have to be reset to zero during its operation, and more specifically to provide one which is able to continuously integrate input data signals without interruption. It would also be desirable to provide such an integrator which can integrate both positive and negative input signals regardless of the magnitude of these signals, within reasonable limits.